1. Technical Field
The present invention relates to a Phase Locked Loop (PLL), and more particularly to a PLL with an improved phase lock/unlock detection function.
2. Discussion of the Related Art
A Cathode Ray Tube (CRT) monitor is a representative example of the peripheral equipment used with a computer for displaying video signals (e.g., R, G, B) on a screen, according to a horizontal synchronization signal H_Sync and a vertical synchronization signal V_Sync transmitted from a video card of the computer.
When the mode of the CRT monitor switches or power is turned on or off, a transient phenomena occurs in which the frequencies of the horizontal synchronization signal H_Sync and vertical synchronization signal V_Sync vary significantly. This transient phenomena typically induces a surge voltage, resulting in a voltage that can destroy components such as diodes, transistors, etc.
An example of the mode being switched in a CRT monitor is when there is a switch from DOS mode to Windows mode. In DOS mode, the frequency of the horizontal synchronization signal H_Sync is about 31 kHz and in Windows mode, the frequency is about 68 kHz. As described above, when the mode of the CRT monitor is switched, frequency variations of the horizontal synchronization signal H_Sync and the vertical synchronization signal V_Sync are significant.
While this is taking place a PLL generates a clock pulse signal with a predetermined frequency from the horizontal synchronization signal H_Sync and the vertical synchronization signal V_Sync, according to a Microcomputer (Micom), and further controls the vertical deflection and horizontal deflection of an electron beam. The PLL additionally provides phase lock/unlock information to the Micom, which allows the Micom to perform controlling functions according to the phase lock/unlock information. The frequency variation of the horizontal synchronization signal H_Sync and the vertical synchronization signal V_Sync generates a phase unlock of the PLL. The Micom can recognize the mode of the switching state of the CRT monitor according to the phase unlock information received from the PLL. If the Micom recognizes the mode of the switching state, the Micom will suppress an abnormally high voltage (e.g., a surge voltage).
Accordingly, quick phase unlock detection by the PLL is important for allowing the Micom to quickly perform, for example, a voltage suppression, when the mode of the CRT monitor is switched.
An example of a PLL with a phase lock/unlock detection function is disclosed in U.S. Pat. No. 6,133,769, issued Oct. 17, 2000, entitled “Phase Locked Loop With A Lock Detector.” A PLL with a phase lock/unlock detection function will be described in detail with reference to FIGS. 1-3.
Referring to FIG. 1, a PLL 10 includes a Phase Frequency Detector (PFD) 11, a charge pump 12, a loop filter 13, a Voltage Controlled Oscillator (VCO) 14, a divider 15, and a phase lock/unlock detection circuit 16.
The PFD 11 compares a phase and frequency of an input synchronization signal SIN to the phase and frequency of a reference synchronization signal SREF, and generates an up signal UP or a down signal DN.
The charge pump 12 controls a charge or discharge of the loop filter 13 according to the up signal UP or the down signal DN. The output frequency of the VCO 14 is determined according to the loop voltage of the loop filter 13. The VCO 14 outputs a predetermined clock pulse signal SOUT with the frequency determined according to the loop voltage.
The divider 15 divides the clock pulse signal SOUT and outputs the reference synchronization signal SREF. The phase lock/unlock detection circuit 16 monitors the output of the up signal UP or down signal DN, detects a phase lock/unlock state, and outputs a detection signal DET to a Micom (not shown).
The configuration and operation of the phase lock/unlock detection circuit 16 will now be described with reference to FIG. 2.
Referring to FIG. 2, the phase lock/unlock detection circuit 16 includes a NOR gate 17, current sources I1 and I2, a switching unit 18, a capacitor C1, and a comparator 19.
The NOR gate 17 receives and performs a NOR-operation on an up signal UP and a down signal DN. The switching unit 18 is connected between the current source I1 and a NODE 1, and the current source 12, and is turned on or turned off by the output signal of the NOR gate 17.
The capacitor C1 receives electric charge(s) from the current source 11 via the node NODE1 when the switching unit 18 is turned off.
The comparator 19 compares a voltage VC of the node NODE1 to a predetermined reference voltage VREF, and outputs a detection signal DET at a “high” or “low” level. To allow the comparator 19 to stably detect phase lock/unlock information, the reference voltage VREF has a hysteresis characteristic and the current source 11 is set to a small value. As a result, a time delay exists from the initial generation of phase unlock to the detection of the phase unlock by the comparator 19.
The operation of the phase lock/unlock detection circuit 16 in the PLL 10, will now be described with reference to FIG. 3.
Referring to FIG. 3, the PFD 11 generates an up signal UP or down signal DN when a phase difference is generated between the input synchronization signal SIN and the reference synchronization signal SREF.
The level of the voltage VC of the node NODE1 increases gradually according to the up signal UP or down signal DN. The comparator 19 outputs a detection signal DET at a “high” level when the level of the voltage VC is higher than that of a high reference voltage VREFH.
The charge pump 12 controls charge or discharge of the loop filter 13 according to the up signal UP or down signal DN, and the VCO 14 controls the output frequency of the clock pulse signal SOUT according to the loop voltage of the loop filter 13. By operating the PLL 10 as such, the phase difference between the input synchronization signal SIN and the reference synchronization signal SREF is gradually reduced, and the output count of the up signal UP or the down signal DN is gradually reduced.
As a result, the capacitor C1 of the phase lock/unlock detection circuit 16 is discharged and the level of the voltage VC of the node NODE1 is gradually lowered as shown in FIG. 3.
As further shown in FIG. 3, the comparator 19 outputs a detection signal DET at a “low” level when the level of the voltage VC is lower than that of a low reference voltage VREFL. When this occurs, a Micom (not shown) determines a phase unlocked state if the detection signal DET is “high” and a phase locked state if the detection signal is “low”.
However, since the phase lock/unlock detection circuit of the PLL 10 detects a phase unlock after a delay time TD of dozens of ms (millisecond) elapses from an initial generation U of the phase unlock, it is difficult to quickly provide phase unlock information to the Micom in communication with the PLL 10. As a result, a problem exists in that the Micom cannot quickly perform a control operation such as suppressing a surge voltage, etc. when the mode of a CRT monitor is switched.